Pulse generators generate output pulses with arbitrary start and stop times. Generally, the leading edges of two trigger signals, START and STOP, determine the pulse start and stop times. The trailing edges of trigger signals should have no effect upon the pulse generator's output pulse width. Combinations of synchronous delay line (SDL) tap outputs typically provide pulse generator trigger signals. Six basic combinations of trigger timings, as shown in FIG. 1, can be generated usign SDL taps. The leading edges are shown as rising edges. However, without any loss of generality, the leading edges could be both falling edges or some combination of rising and falling edges. The polarity of the leading edges is entirely a design choice.
There are two types of pulse generators which can be constructed to operate with the trigger signals of FIG. 1: level-sensitive pulse generators and edge-sensitive pulse generators. No type of level-sensitive pulse generaotr wil operate with all six trigger combinations shown in FIG. 1. For example, a simple Set-Reset flip-flop will operate only with the combination of trigger signals shown in FIG. 1A. Other level-sensitive pulse generators operate with some combination of the trigger signals shwon in FIGS. 1B-1D. No level-sensitive pulse generators operates with the combination of trigger signals shwon in FIGS. 1E and 1F.
Only an edge-sensitive pulse generator operates with all six combinations of trigger signals shown in FIG. 1. The relative complexity of edge-sensitive pulse generators counterbalances their versatility. As the complexity of edge-sensitive pulse generators increases so does the input-to-output delay. Complexity of design in integrated circuit pulse generators is often accompanied by a reduction in accuracy and increased input-to-output delay, sensitivity to process, supply voltage and temperature variations.